View PCM1718E2K_7705444.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 pcm1718e tm international airport industrial park ? mailing address: po box 11400, tucson, az 85734 ? street address: 6730 s. tucson blvd., tucson, az 85706 ? tel: (520) 746-1111 ? twx: 910-952-1111 internet: http://www.burr-brown.com/ ? faxline: (800) 548-6133 (us/canada only) ? cable: bbrcorp ? telex: 066-6491 ? fax: (520) 889-1510 ? immediate product info: (800) 548-6132 pcm1718e stereo audio digital-to-analog converter features l accepts 16- or 18-bit i 2 s, or 18-bit normal input data l complete stereo dac: 8x oversampling digital filter multi-level delta-sigma dac analog low pass filter output amplifier l high performance: C90db thd+n 96db dynamic range 100db snr l system clock: 256fs or 384fs l wide power supply: +2.7v to +5.5v l selectable functions: soft mute digital de-emphasis l small 20-pin ssop package description the pcm1718 is a complete low cost stereo, audio digital-to-analog converter, including digital interpo- lation filter, 3rd-order delta-sigma dac, and analog output amplifiers. pcm1718 is fabricated on a highly advanced 0.6 m cmos process. pcm1718 accepts 18- bit normal input data format, or 16- or 18-bit i 2 s data format. the digital filter performs an 8x interpolation func- tion, as well as special functions such as soft mute and digital de-emphasis. pcm1718 is suitable for a wide variety of cost-sensitive consumer applications where good performance is re- quired. its low cost, small size, and single power supply make it ideal for bs tuners, keyboards, mpeg audio, pcmcia audio cards (zv port), midi applications, and set-top boxes. serial input i/f mode control i/f 8x oversampling digital filter with multi function control clock/osc manager xti xto clko v cc agnd v dd dgnd multi-level delta-sigma modulator v out l d/c_l open drain dac multi-level delta-sigma modulator output amp and low-pass filter output amp and low-pass filter v out r d/c_r zero dac dm0 dm1 mute lrcin din bckin reset format rstb power supply pcm1718 ? 1996 burr-brown corporation pds-1325a printed in u.s.a. june, 1996 sbas050
2 pcm1718e specifications all specifications at +25 c, +v cc = +v dd = +5v, fs = 44.1khz, and 18-bit input data, sysclk = 384fs, unless otherwise noted. measurement bandwidth is 20khz. pcm1718e parameter conditions min typ max units resolution 16 18 bits digital input/output logic family cmos input logic level: v ih (2) 70% of v dd v v il (2) 30% of v dd v v ih (3) 70% of v dd v v il (3) 30% of v dd v v ih (4) 64% of v dd v v il (4) 28% of v dd v input logic current: i ih (5) C6.0 m a i il (5) C120 m a i ih (6) C2 m a i il (6) 0.02 m a i ih (4) v in = 3.2v 40 m a i il (4) v in = 1.4v C40 m a output logic level: (+v dd = +5v) v oh (7) i oh = C5ma 3.8 v v ol (7) i ol = +5ma 1.0 v v ol (8) i ol = +5ma 1.0 v interface format selectable normal, i 2 s data format 16/18 bits msb first binary twos complement sampling frequency 32 44.1 48 khz system clock frequency 256fs/384fs 8.192/12.288 11.2896/16.9344 12.288/18.432 mhz dc accuracy gain error 1.0 5.0 % of fsr gain mismatch channel-to-channel 1.0 5.0 % of fsr bipolar zero error v o = 1/2 v cc at bipolar zero 30 mv dynamic performance (1) v cc = +5v, f = 991hz thd+n at fs (0db) C90 C80 db thd+n at C60db C34 db dynamic range eiaj, a-weighted 90 96 db signal-to-noise ratio eiaj, a-weighted 92 100 db channel separation 90 97 db level linearity error (C90db) 0.5 db dynamic performance (1) v cc = +3v, f = 991hz thd+n at fs (0db) C86 db dynamic range eiaj, a-weighted 91 db signal-to-noise ratio eiaj, a-weighted 94 db digital filter performance pass band ripple 0.17 db stop band attenuation C35 db pass band 0.445 fs stop band 0.555 fs de-emphasis error (fs = 32khz ~ 48khz) C0.2 +0.55 db delay time (latency) 11.125/fs sec analog output voltage range fs (0db) out 62% of v cc vp-p load impedance 5k w center voltage 50% of v cc v power supply requirements voltage range: +v cc +2.7 +5.5 vdc +v dd +2.7 +5.5 vdc supply current: +i cc +i dd (9) +v cc = +v dd = +5v 18.0 25.0 ma +v cc = +v dd = +3v 9.0 15.0 ma power dissipation +v cc = +v dd = +5v 90 125 mw +v cc = +v dd = +3v 27 45 mw temperature range operation C25 +85 c storage C55 +100 c notes: (1) tested with shibasoku #725 thd. meter 400hz hpf, 30khz lpf on, average mode with 20khz bandwidth limiting. (2) pins 4, 5, 6, 14: lrcin, din, bckin, format. (3) pins 15, 16, 17, 18: rstb, dm0, dm1, mute (schmitt trigger input). (4) pin 1: xti. (5) pins 15, 16, 17, 18: rstb, dm0, dm1, mute (if pull-up resistor is used). (6) pins 4, 5, 6: lrcin, din, bckin (if pull-up resistor is not used). (7) pin 19: clko. (8) pin 7: zero. (9) no load on pins 19 (clko) and 20 (xto).
3 pcm1718e pin assignments pin configuration package information package drawing product package number (1) pcm1718e 20-pin ssop 334-1 note: (1) for detailed drawing and dimension table, please see end of data sheet, or appendix c of burr-brown ic data book. absolute maximum ratings power supply voltage ....................................................................... +6.5v +v cc to +v dd difference ................................................................... 0.1v input logic voltage .................................................. C0.3v to (v dd + 0.3v) power dissipation .......................................................................... 200mw operating temperature range ......................................... C25 c to +85 c storge temperature ........................................................ C55 c to +125 c lead temperature (soldering, 5s) .................................................. +260 c thermal resistance, q ja ....................................................................................... +70 c/w xti dgnd v dd lrcin din bckin zero d/c_r v out r agnd xto clko mute dm1 dm0 rstb format dc_l v out l v cc 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 top view ssop pin name function data input interface pins 4 lrcin sample rate clock input. controls the update rate (fs). 5 din serial data input. msb first, right justified (sony format, 18 bits) or i 2 s (philips format, 16 or 18 bits). 6 bckin bit clock input. clocks in the data present on din input. mode control and clock signals 1 xti oscillator input (external clock input). for an internal clock, tie xti to one side of the crystal oscillator. for an external clock, tie xti to the output of the chosen external clock. 14 (1) format a high selects i 2 s input data format, and a low selects normal (sony) input data format. 16 (1) dm0 de-emphasis selection. 17 (1) dm1 de-emphasis selection. 18 (1) mute soft mute control. when set low, the outputs are muted. 19 clko buffered output of oscillator. equivalent to xti. 20 xto oscillator output. when using the internal clock, tie to the opposite side (from pin 1) of the crystal oscillator. when using an external clock, leave xto open. operational controls and flags 7 zero infinite zero detection flag, open drain output. when the input is continuously zero for 65,536 cycles of bckin, zero is low. 15 (1) rstb resets dac operation with an active low pulse. analog output functions 8 d/c_r right channel output amplifier common. bypass to ground with 10 m f capacitor. 9v out r right channel analog output. v out max = 0.62 x v cc . 12 v out l left channel analog output. v out max = 0.62 x v cc . 13 d/c_l left channel output amplifier common. bypass to ground with 10 m f capacitor. power supply connections 2 dgnd digital ground. 3v dd digital power supply (+5v or +3v). 10 agnd analog ground. 11 v cc analog power supply (+5v or +3v). note: (1) with internal pull-up. the information provided herein is believed to be reliable; however, burr-brown assumes no responsibility for inaccuracies or omissions. burr-brown assumes no responsibility for the use of this information, and all use of such information shall be entirely at the users own risk. prices and specifications are subject to change without notice. no patent rights or licenses to any of the circuits described herein are implied or granted to any third party. burr-brown does not authorize or warrant any burr-brown product for use in life support devices and/or systems.
4 pcm1718e dynamic range and snr vs v cc , v dd f in = 1khz, 384fs v cc , v dd (db) 100 98 96 94 92 90 3.5 4.0 4.5 5.0 5.5 6.0 snr dynamic range thd+n vs input data f in = 1khz, fs (0db) input data thd+n (db) ?4 ?6 ?8 ?0 ?2 ?4 16-bit 18-bit 256fs 384fs thd+n vs temperature f in = 1khz, 384fs temperature (?) thd+n at fs (db) thd+n at ?0db (db) ?4 ?6 ?8 ?0 ?2 ?0 ?0 ?4 ?8 ?5 0 25 50 75 85 100 ?0db 0db dynamic range vs input data f in = 1khz input data dynamic range (db) 100 98 96 94 92 90 16-bit 18-bit 256fs 384fs thd+n vs v cc , v dd f in = 1khz, 384fs v cc , v dd (v) thd+n at fs (db) thd+n at ?0db (db) ?4 ?6 ?8 ?0 ?2 ?4 ?0 ?4 ?8 3.5 4.0 4.5 5.0 5.5 6.0 ?0db 0db typical performance curves at t a = +25 c, v s = +5v, r l = 100 w , c l = 2pf, and r fb = 402 w, unless otherwise noted. dynamic performance
5 pcm1718e 0 0.4536fs 1.3605fs 2.2675fs 3.1745fs 4.0815fs 0 ?0 ?0 ?0 ?0 ?00 db overall frequency characteristic frequency (hz) typical performance curves at t a = +25 c, v s = +5v, r l = 44.1khz, f sys = 384fs, and 18-bit input data, unless otherwise noted. digital filter 0 5k 10k 15k 20k 25k 0 C2 C4 C6 C8 C10 C12 level (db) frequency (hz) de-emphasis frequency response (32khz) de-emphasis frequency response (44.1khz) 0 C2 C4 C6 C8 C10 C12 level (db) 0 5k 10k 15k 20k 25k frequency (hz) de-emphasis frequency response (48khz) 0 C2 C4 C6 C8 C10 C12 level (db) frequency (hz) 0 5k 10k 15k 20k 25k 0 3628 7256 10884 14512 0.6 0.4 0.2 0 C0.2 C0.4 C0.6 frequency (hz) de-emphasis error (32khz) error (db) 0 4999.8375 9999.675 14999.5125 19999.35 0.6 0.4 0.2 0 C0.2 C0.4 C0.6 frequency (hz) de-emphasis error (44.1khz) error (db) 0 5442 10884 16326 21768 0.6 0.4 0.2 0 C0.2 C0.4 C0.6 frequency (hz) de-emphasis error (48khz) error (db) passband ripple characteristic 0 ?.2 ?.4 ?.6 ?.8 ? 0 0.1134fs 0.2268fs 0.3402fs 0.4535fs db frequency (hz)
6 pcm1718e c 1 c 2 c 1 , c 2 = typ 22pf internal system clock xti x?al xto pcm1718e clko external clock internal system clock xti xto pcm1718e external clock input xto pin = no connection crystal resonator connection clko system clock the system clock for pcm1718 must be either 256fs or 384fs, where fs is the audio sampling frequency (typically 32khz, 44.1khz, or 48khz). the system clock is used to operate the digital filter and the modulator. the system clock can be either a crystal oscillator placed between xti (pin 1) and xto (pin 20), or an external clock input to xti. if an external system clock is used, xto is open (floating). figure 1 illustrates the typical system clock connections. pcm1718 has a system clock detection circuit which auto- matically senses if the system clock is operating at 256fs or 384fs. the system clock should be synchronized with lrcin (pin 4) clock. lrcin (left-right clock) operates at the sampling frequency fs. in the event these clocks are not synchronized, pcm1718 can compensate for the phase dif- ference internally. if the phase difference between left-right and system clocks is greater than 6 bit clocks (bckin), the synchronization is performed internally. while the synchro- nization is processing, the analog output is forced to a dc level at bipolar zero. the synchronization typically occurs in less than 1 cycle of lrcin. data interface formats digital audio data is interfaced to pcm1718 on pins 4, 5, and 6lrcin (left-right clock), din (data input) and bckin (bit clock). pcm1718 can accept both normal and i 2 s data formats. normal data format is msb first, twos complement, right-justified. i 2 s data is compatible with philips serial data protocol. figures 3 and 4 illustrate the input data formats. figure 1. internal clock circuit diagram and oscillator connection. figure 2. external clock timing requirements. t xtih t xtil 1/256fs or 1/384fs 64% of v dd 28% of v dd external system clock high t xtih 10ns (min) external system clock low t xtil 10ns (min) function control pin data input format format (pin 14) normal i 2 s de-emphasis dm0, dm1 (pins 16, 17) 32khz 44.1khz 48khz soft mute mute (pin 18) reset rstb (pin 15) functional controls pcm1718 allows the user to control the input data format, soft mute, and digital de-emphasis frequency. table i illus- trates the selectable functions: table i. selectable functions.
7 pcm1718e din (pin 5) lrcin (pin 4) bckin (pin 6) left-channel data right-channel data 1 f/s audio data word = 18-bit 18 16 msb lsb msb lsb 17 18 123 18 16 17 123 16 17 figure 3. normal data input timing. figure 4. i 2 s data input timing. bckin pulsewidth (high level) t bch 50ns (min) bckin pulsewidth (low level) t bcl 50ns (min) bckin pulse cycle time t bcy 100ns (min) bckin rising edge y lrcin edge t bl 30ns (min) lrcin edge y bckin rising edge t lb 30ns (min) din setup time t ds 30ns (min) din hold time t dh 30ns (min) figure 5. data input timing. t bch t bcl t lb t bcy t bl t dh t ds 50% of v dd 50% of v dd 50% of v dd lrcin bckin din data format a high on pin 14 (format) sets the input format to i 2 s, and a low sets the format to normal (msb-first, right-justified sony format). soft mute a low on pin 18 (mute) causes both outputs to be muted. this muting is done in the digital domain so there is no audible click when the soft mute is enacted. de-emphasis pcm1718 allows for digital de-emphasis for all three stan- dard sampling frequencies: dm1 (pin 17) dm0 (pin 16) de-emphasis mode 0 0 off 0 1 48khz 1 0 44.1khz 1 1 32khz din (pin 5) din (pin 5) audio data word = 16-bit lrcin (pin 4) bckin (pin 6) 16 14 msb lsb msb lsb left-channel data right-channel data 1 f/s 15 123 16 14 15 123 audio data word = 18-bit 18 16 msb lsb msb lsb 17 123 18 16 17 123 12 12
8 pcm1718e 1024 system (= xti) clocks reset reset removal 2.6v 2.2v 1.8v v cc /v dd internal reset xti clock figure 6. internal power-on reset timing. figure 7. rstb-pin reset timing. reset pcm1718 has both internal power on reset circuit and the rstb-pin (pin 15) which accepts external forced reset by rstb = low. for internal power on reset, initialize (reset) is done automatically at power on v dd >2.2v (typ). during internal reset = low, the output of the dac is invalid and the analog outputs are forced to v cc /2. figure 6 illustrates the timing of internal power on reset. for the rstb-pin, pstb-pin accepts external forced reset by rstb = l. during rstb = l, the output of the dac is invalid and the analog outputs are forced to v cc /2 after internal initialize (1024 system clocks count after rstb = h.) figure 7 illustrates the timing of rstb-pin reset. figure 8. typical connection diagram of pcm1718. 1 20 4 5 6 14 18 17 16 15 xti xto lrcin din bckin format mute dm1 dm0 rstb clko v out r d/c_r d/c_l v out l zero 19 9 8 13 12 7 format control reset pcm audio data processor to external mute circuit 10? v dd 4.7k w + fout = inverted xti (1 pin) to other system +5v or +3 analog power supply post low pass filter post low pass filter 10? + 0.1? ~ 10? bypass capacitor 23 dgnd v dd 10 11 agnd v cc 0.1? ~ 10? bypass capacitor 10pf ~ 22pf 10pf ~ 22pf (optional) (optional) 1024 system (xti) clocks reset reset removal xti clock internal reset rstb-pin 50% of v dd t rst (1) note: (1) t rst = 20ns min
9 pcm1718e figure 10. 5-level ds modulator block diagram. power supply connections pcm1718 has two power supply connections: digital (v dd ) and analog (v cc ). each connection also has a separate ground. if the power supplies turn on at different times, there is a possibility of a latch-up condition. to avoid this condi- tion, it is recommended to have a common connection between the digital and analog power supplies. if separate supplies are used without a common connection, the delta between the two supplies during ramp-up time must be less than 0.6v. an application circuit to avoid a latch-up condition is shown in figure 9. dgnd agnd v dd v cc digital power supply analog power supply figure 9. latch-up prevention circuit. bypassing power supplies the power supplies should be bypassed as close as possible to the unit. refer to figure 8 for optimal values of bypass capacitors. theory of operation the delta-sigma section of pcm1718 is based on a 5-level amplitude quantizer and a 3rd-order noise shaper. this section converts the oversampled input data to 5-level delta- sigma format. a block diagram of the 5-level delta-sigma modulator is shown in figure 10. this 5-level delta-sigma modulator has the advantage of stability and clock jitter sensitivity over the typical one-bit (2 level) delta-sigma modulator. the combined oversampling rate of the delta-sigma modu- lator and the internal 8-times interpolation filter is 48fs for a 384fs system clock, and 64fs for a 256fs system clock. the theoretical quantization noise performance of the 5-level delta-sigma modulator is shown in figure 11. 20 0 ?0 ?0 ?0 ?0 ?00 ?20 ?40 ?60 3rd-order ds modulator frequency (khz) 0 5 10 15 20 gain (?b) 25 figure 11. quantization noise spectrum. out 48fs (384fs) 64fs (256fs) in 8fs 18-bit + + + 4 3 2 1 0 5-level quantizer + + z ? + + z ? + + z ?
10 pcm1718e 10k w 10k w 10k w 1500pf 100pf 680pf + v sin 90 0 ?0 ?80 ?70 ?60 100 1k 10k 100k 1m gain vs frequency frequency (hz) phase (? 6 ?4 ?4 ?4 ?4 ?4 gain (db) gain phase opa604 application considerations delay time there is a finite delay time in delta-sigma converters. in a/d converters, this is commonly referred to as latency. for a delta-sigma d/a converter, delay time is determined by the order number of the fir filter stage, and the chosen sampling rate. the following equation expresses the delay time of pcm1718: t d = 11.125 x 1/fs for fs = 44.1khz, t d = 11.125/44.1khz = 251.4 m s applications using data from a disc or tape source, such as cd audio, cd-interactive, video cd, dat, minidisc, etc., generally are not affected by delay time. for some profes- sional applications such as broadcast audio for studios, it is important for total delay time to be less than 2ms. output filtering for testing purposes all dynamic tests are done on the pcm1718 using a 20khz low pass filter. this filter limits the measured bandwidth for thd+n, etc. to 20khz. failure to use such a filter will result in higher thd+n and lower snr and dynamic range readings than are found in the specifications. the low pass filter removes out of band noise. although it is not audible, it may affect dynamic specification numbers. the performance of the internal low pass filter from dc to 24khz is shown in figure 12. the higher frequency rolloff of the filter is shown in figure 13. if the users application has the pcm1718 driving a wideband amplifier, it is recom- mended to use an external low pass filter. a simple 3rd- order filter is shown in figure 14. for some applications, a passive rc filter or 2nd-order filter may be adequate. 10 5 0 ? ?0 ?5 ?0 ?5 ?0 ?5 ?0 ?5 ?0 ?5 10 100 1k 10k 100k 1m 10m frequency (hz) db ?0 internal analog filter frequency response (10hz~10mhz) figure 13. low pass filter frequency response. 1.0 0.5 0 ?.5 ?.0 db 20 frequency (hz) 100 1k 10k 24k internal analog filter frequency response (20hz~24khz, expanded scale) figure 12. low pass filter frequency response. figure 14. 3rd-order lpf.
11 pcm1718e figure 15. test block diagram. test conditions figure 15 illustrates the actual test conditions applied to pcm1718 in production. the 11th-order filter is necessary in the production environment for the removal of noise resulting from the relatively long physical distance between the unit and the test analyzer. in most actual applications, the 3rd-order filter shown in figure 14 is adequate. under normal conditions, thd+n typical performance is C70db with a 30khz low pass filter (shown here on the thd meter), improving to C89db when the external 20khz 11th- order filter is used. for cost-sensitive applications, a single rc filter, as shown in figure 18, may be adequate. evaluation fixtures dem-pcm1718 this evaluation fixture is primarily intended for quick evalu- ation of the pcm1718s performance. dem-pcm1718 can accept either an external clock or a user-installed crystal oscillator. all of the functions can be controlled by on-board switches. dem-pcm1718 does not contain a receiver chip or an external low pass filter. dem-pcm1718 requires a single +2.7v to +5v power supply. out-of-band noise considerations delta-sigma dacs are by nature very sensitive to jitter on the master clock. phase noise on the clock will result in an increase in noise, ultimately degrading dynamic range. it is difficult to quantify the effect of jitter due to problems in synthesizing low levels of jitter. one of the reasons delta- sigma dacs are prone to jitter sensitivity is the large quantization noise when the modulator can only achieve two discrete output levels (0 or 1). the multi-level delta-sigma dac has improved theoretical snr because of multiple output states. this reduces sensitivity to jitter. figure 16 contrasts jitter sensitivity between a one-bit pwm type dac and multi-level delta-sigma dac. the data was derived using a simulator, where clock jitter could be completely synthesized. pga digital lch rch dem- pcm1718 cd player dai 11th-order lpf thd meter 0db/60db 30khz lpf on through for test of s/n ratio and dynamic range, a-filter on. test disk shibasoku #725 0 100 200 300 400 500 600 110 105 100 95 90 85 80 75 70 65 60 dynamic range (db) clock jitter (ps) multi-level pwm figure 16. simulation results of clock jitter sensitivity. figure 17. simulation method for clock jitter. 2 1 0 ? 2 48fs 14.4ps 1k w 1800pf pcm1718 output f c = 88khz figure 18. rc output filter.
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) pcm1718e active ssop db 20 65 green (rohs & no sb/br) cu nipdau level-1-260c-unlim pcm1718e/2k active ssop db 20 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim pcm1718e/2kg4 active ssop db 20 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim pcm1718eg4 active ssop db 20 65 green (rohs & no sb/br) cu nipdau level-1-260c-unlim (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 11-dec-2006 addendum-page 1
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant pcm1718e/2k ssop db 20 2000 330.0 17.4 8.5 7.6 2.4 12.0 16.0 q1 package materials information www.ti.com 13-jun-2008 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) pcm1718e/2k ssop db 20 2000 336.6 336.6 28.6 package materials information www.ti.com 13-jun-2008 pack materials-page 2
important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third-party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of ti information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. information of third parties may be subject to additional restrictions. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. ti products are not authorized for use in safety-critical applications (such as life support) where a failure of the ti product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of ti products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by ti. further, buyers must fully indemnify ti and its representatives against any damages arising out of the use of ti products in such safety-critical applications. ti products are neither designed nor intended for use in military/aerospace applications or environments unless the ti products are specifically designated by ti as military-grade or "enhanced plastic." only products designated by ti as military-grade meet military specifications. buyers acknowledge and agree that any such use of ti products which ti has not designated as military-grade is solely at the buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. ti products are neither designed nor intended for use in automotive applications or environments unless the specific ti products are designated by ti as compliant with iso/ts 16949 requirements. buyers acknowledge and agree that, if they use any non-designated products in automotive applications, ti will not be responsible for any failure to meet such requirements. following are urls where you can obtain information on other texas instruments products and application solutions: products applications amplifiers amplifier.ti.com audio www.ti.com/audio data converters dataconverter.ti.com automotive www.ti.com/automotive dsp dsp.ti.com broadband www.ti.com/broadband clocks and timers www.ti.com/clocks digital control www.ti.com/digitalcontrol interface interface.ti.com medical www.ti.com/medical logic logic.ti.com military www.ti.com/military power mgmt power.ti.com optical networking www.ti.com/opticalnetwork microcontrollers microcontroller.ti.com security www.ti.com/security rfid www.ti-rfid.com telephony www.ti.com/telephony rf/if and zigbee? solutions www.ti.com/lprf video & imaging www.ti.com/video wireless www.ti.com/wireless mailing address: texas instruments, post office box 655303, dallas, texas 75265 copyright ? 2008, texas instruments incorporated

▲Up To Search▲

Price & Availability of PCM1718E2K

	To Download PCM1718E2K Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .